Non-volatile data storage devices, such as universal serial bus (USB) flash memory devices or removable storage cards, have allowed for increased portability of data and software applications. Flash memory devices can enhance data storage density by storing multiple bits in each flash memory cell. For example, Multi-Level Cell (MLC) flash memory devices provide increased storage density by storing 3 bits per cell, 4 bits per cell, or more. Although increasing the number of bits per cell and reducing device feature dimensions may increase a storage density of a memory device, a bit error rate of data stored at the memory device may also increase.
Error correction coding (ECC) is often used to correct errors that occur in data read from a memory device. Prior to storage, data may be encoded by an ECC encoder to generate redundant information (e.g. “parity bits”) that may be stored with the data as an ECC codeword. As more parity bits are used, an error correction capacity of the ECC increases and a number of bits required to store the encoded data also increases.
One source of errors that occur in data stored in a memory device is a result of repeated write/erase (W/E) cycles to the memory device. Erasing a block of flash memory conventionally includes performing an “erase loop” that includes applying an erase pulse (e.g., applying an erase voltage to the erase block and removing the erase voltage), and reading the storage elements of the block. The erase loop may be repeated until all storage elements of the block have transitioned to an erased state. A number of erase pulses that are applied during each erase operation may depend of various factors, such as a physical condition of storage elements of the block and/or characteristics of data that is stored in the block. Cell threshold voltage distributions (CVDs) may shift and broaden with increasing numbers of W/E cycles, resulting in an increasing number of data errors as the memory device ages. Wear leveling techniques may be used to distribute W/E operations so that all regions of the memory are subjected to approximately an equal number of W/E cycles. As a result, wear leveling may extend a useful life of the memory device that may otherwise be limited by a portion of the memory that experiences accelerated wearing due to more frequent erase operations as compared to other portions of the memory.
However, tracking W/E cycles may provide incomplete information regarding the condition of individual erase blocks. For example, some blocks having a relatively high W/E count may reliably store data due to a low amount of wear, while some blocks having a relatively low W/E count may have reduced reliability, such as when a grown defect occurs. Managing a data storage device based on incomplete information provided by tracking W/E cycles may reduce performance and/or a useful life of the data storage device as compared to managing the data storage device based on more complete information.